Set FDM Info
更新时间： 2026/08/06
在Gitcode上查看源码Set FDM Info
Change History
| openUBMC Version | Revision Date | Description |
|---|---|---|
| 25.06 | 2025/06/26 | Initial draft: add command details |
Basic Information
Function Description
This command is used to set auxiliary fault diagnosis information.
Privilege
DiagnoseMgnt
Command Information
Request Information
| Byte | Data Field |
|---|---|
| NetFn | 30h |
| CMD | 92h |
| 1:3 | Manufacturer ID, LS Byte first. The length is fixed to three bytes. For example, if the vendor ID is 2011 and the corresponding hexadecimal value is 0x0007DB, the first byte is DBh, the second byte is 07h, and the third byte is 00h. |
| 4 | Sub command, subcommand = 17h |
| 5 | FDM-related configuration parameters. For details, see Table 1. |
| 6 | Data length. |
| 7:N | Written data |
Response Information
| Byte | Data Field |
|---|---|
| 1 | Completion Code |
| 2:4 | Manufacturer ID, LS Byte first. The length is fixed to three bytes. For example, if the vendor ID is 2011 and the corresponding hexadecimal value is 0x0007DB, the first byte is DBh, the second byte is 07h, and the third byte is 00h. |
Reference
Table 1 FDM configuration parameters
| Parameter | Parameter Data | No. (Decimal) |
|---|---|---|
| CPU BusNO. (write only) | data1: CPU Count (maximum number of CPUs supported by a platform) data2:N Bus Start Address (Bus 0 of each CPU is reported in sequence, for example, CPU0Bus0, CPU1Bus0, CPU2Bus0, CPU3Bus0......) dataN+1:2N-1 Bus Size The number of buses assigned to each CPU is reported in sequence. If all the 256 buses are evenly assigned, the value of these fields is 0x40 for servers with four processors and 0x20 for servers with eight processors. | 1 |
| Setup Status (read write) | data1- FDM Enable 0:Disable 1:Enable 0xff:NA data2-EMCA/EMCA2 0:Disable 1:Enable 0xff:NA data3-IOMCA 0:Disable 1:Enable 0xff:NA data4-Viral 0:Disable 1:Enable 0xff:NA data5-CDC 0:Disable 1:Enable 0xff:NA data6-System Error 0:Disable 1:Enable 0xff:NA data7:8-Reserved Default value 0xFF | 2 |
| PlatForm (write only) | data1 0: Unknow 1: Sandy Brige 2: Ivy Brige 3: HasWell 6: icelake | 3 |
| MCE RegVal (write only) | data1: 2-RegNo register address. Some MCE registers cannot be obtained through the ME and can only be reported by the BIOS. data3:10 RegVal register value ...... (The register addresses and register values are arranged in a loop.) MaxLength 240Bytes | 4 |
| PCIE Addr Info (write only) | data1:1: status code data2:n: data. For details, see Table 2. | 5 |
| Memory Addr Info (write only) | data1:1: status code Data2:1-Type: Before Purley: 1-SAD, 2-TAD, 3-RIR Purley (including cooplake): 0x10, 0x11, 0x12, 0x13-SAD, 0x20-TAD, 0x30, 0x31, 0x32 - RIR Whitley(IceLake): 0x40, 0x41, 0x42, 0x43, 0x44-SAD, 0x50, 0x51-TAD, 0x60, 0x61 – RIR, 0x70 – Platform ARM (1620): 0x80-HHA_INTLV, 0x81-DDRC_INTLV data3:n: data. For details, see Table 3. | 6 |
| FDM Version (read only) | data1: 1-main version of the FDM version, 1-FDM 1.0, 2-FDM 2.0, and so on data2:1: secondary version of the FDM version. The value starts from 0. | 7 |
| IERR Status | data1:1: indicates whether an IERR occurs. When an IERR occurs, the system is manually or automatically hot reset. Then the BIOS collects fault data and reports the data to the BMC. When an IERR occurs, the BIOS needs to perform a cold reset on the system to ensure that the initialization is complete. This parameter is used to notify the BIOS that IERR has occurred recently. After the BIOS reports the fault data, the system is cold reset. 0- No IERR occurs. 1- IERR occurred | 8 |
| CPU Threads Info | data1:1-socket_id data2:n: thread information of the corresponding socket | 9 |
| Address Space Info | data1:1: address type: 1: TF address segment data2:8: start address, with the lower byte before the lower byte Data10:8-address range, with the lower byte before the lower byte | 10 |
| CPU Threads Info (whitley-icelake) | data1:1-socket_id data2:1-core count data3:1-Hyper Thread //Whether Hyper Thread is enabled The value of data4:n-ThreadsID[cores] //cores ranges from 0 to core count-1. For details about the reported value, see MSR:0x53. Only the Thread0 ID information is reported. | 11 |
| Reg Report Version | data1:1-sub_cmd 0x21 data2: 1 indicates that the version number of the ARM register can be reported. (2021.8.12, VERSION_1: DDRC_V2 supported) | 13 |
| Integrated PCIe Addr Info (write only) | Reports the BDF information of the PCIe controller integrated in the socket. data1:1-Socket: logical ID of the CPU. The value starts from 0. data2:1-Report Controller Count: number of reported PCIe controller information records. Enter the actual number of reported records. data3:1-Integrated Controller Type: PCIe controller type. 0: PCIe core; 1: PCIe NIC controller; 2: PCIe NIC controller; 3: PCIe SAS controller; 4: PCIe SATA controller; 5: PCIe ZIP controller; 6: PCIe SEC controller; data4:1-Integrated Controller Index: index of the data3 type. The value range is [0, 1, 2, ..., n]. data5:1-Bus data6:1-Device data7:1-Function data8:12: indicates the information about the second controller. The format is the same as that of data3:7. datan:n+4-: The format is the same as that of data3:7, indicating the information about the nth controller. | 14 |
| Device Health Status (read only) | Querying the NPU Health Status data1:1: queries the number of dev_types. data2:n: dev_type list to be queried, NPU (0), XPU_CARRIER_BOARD (1) Response: data1:1: number of queried devices data2:1: device dev_type data3:1 - device ID data4: 1 indicates the health status. 0: Good; 1: Degrade; 2: Fail; 255: Unknow data5:1: reserved field data6:4: indicates the health status of the second device to be queried. The format is the same as that of data2:5. datan:n+4-The format is the same as that of data2:5, indicating the health status of the nth device to be queried. | 16 |
| Memory Controller Configuration (write only) | Reporting Memory Configuration Information data1:1-Platform Id: used to distinguish different CPU IDs for different platforms. data2: 1-Memory Controller Type: CPU memory controller type. 0: DDRC; 1: HBMC. data3:1: status code; 1: start; 2: reporting; 3: end; 4: hot swap memory address update ends. data4: 1-type: 1-interleaving configuration information of the memory controller data5:n: data. For details, see the 9-4 table. | 17 |
| MultiSystem Memory Space Info (write only) | Reporting Memory Configuration Parameters of Multiple Systems data1:1-Global System Id: global system ID data2:1 - Local System Id: local system ID data3:1-Soc ID: used to distinguish different chip platform generations. data4: 1-Memory Controller Type: memory controller type. 0: DDRC; 1: HBMC. data5: 1-State: status code. 1: reporting started; 2: reporting in progress; 3: reporting ended. data6: 1-Data Type: data type. For details, see Table 4. data7:n-Data: data. For details, see Table 4. | 18 |
| MultiSystem Address Config Info (write only) | Reporting the Configuration of the System Address Space of Multiple Systems data1:1-Global System Id: global system ID data2:1 - Local System Id: local system ID data3:1-Address Type: address type. For details, see Table 5. data4:n-Data: data. For details, see Table 5. | 19 |
| MultiSystem PCIe Addr Info (write only) | Reporting PCIe Configuration Resources of Multiple Systems data1:1-Global System Id: global system ID data2:1 - Local System Id: local system ID data3:n-Data: data. For details, see Table 2. | 20 |
| Bios Report Memory RAS Resource | Reporting Memory Fault Tolerance Resource Information data1:1 - Source Type: resource type. 0: ACLS resource quantity; 1: PPR resource granularity. data2:1 – Global System Id: global system number data3:1 – Local System Id: local system number data4:n – data. For details, see Table 6. | 21 |
Table 2 PCIE Address Parameter
| Status | Data | Status Codes |
|---|---|---|
| Start | N/A | 1 |
| Transmission | data1:1 – Segment //For products with more than eight sockets, such as 9032, different 4-socket servers need to be differentiated. The value 1 indicates that the server is based on the CPU, and the value 0 indicates that the server is not involved. Logical ID of the data2:1 – Socket Id //CPU, starting from 0 data3:1-Bus //Root port BDF corresponding to the PCIe slot data4:1-Device data5:1-Function data6:1-Component Type //When the PCIe slot address information of the PCIe switch is reported, the component type supported by the PCIe slot needs to be reported. For a PCIe slot that is not mounted to the PCIe switch, 0xff is filled in, currently, only the mezzanine cards and standard PCIe cards of some OSCA boards are connected to the PCIe switch. data7:1-Group Id //If duplicate slot IDs exist, use the group ID to distinguish them. The group ID starts from 1. Currently, only the X6800 board has multiple PCIe groups. For other products, the value is 1. When the PCIe slot address information under the PCIe switch is reported, the group ID of the PCIe slot needs to be reported, for the PCIe slot that is not mounted to the PCIe switch, 0xff is filled in. data8:1-Slot Id //When the PCIe slot address information of the PCIe switch is reported, the slot ID of the PCIe slot needs to be reported. For the PCIe slot that is not mounted to the PCIe switch, 0xff is filled in. data9:2 – Vendor Id data11:2 – Device Id data13:1 – SecBus //Secondary Bus Number data14:1 – SubBus; //Subordinate Bus Number data15:1 – BDF No. //BDF sequence number. A component may have one or more BDFs. All the BDFs are reported by sequence number. 0 based data16:1 – Reserved //Reserved byte. Set it to 0 when the BIOS is reported. Indicates the start address of the data17:4 – PciCfg Low Base Addr Start //PCI memory address space in the little endian format. End of the low address in the data21:4 – PciCfg Low Base Addr Start //PCI memory address space, in the little endian format. Upper address of the data25:8 – PciCfg High Base Addr Start //PCI memory address space, in the little endian format. End of the high address in the data33:8 – PciCfg High Base Addr End //PCI memory address space, in the little endian format. data41:3-reserved //Reserved byte. The value is 0 when the BIOS reports data. data44:1 – MMIO Addr Range Count data45:8-MMIO Addr Range0 Base //LS-byte first: little endian. data53:8-MMIO Addr Range0 Len ...... | 2 |
| Reporting the PCIe address information ends in the startup phase. | N/A | 3 |
| The update of the PCIe address information is complete during the running process. | N/A | 4 |
Table 3 Memory Address Parameter
| Status | Type | Data | Status Codes |
|---|---|---|---|
| Start | N/A | N/A | 1 |
| Transmission | SAD(1) | data1:1-socket data2:1 – resv data3:2-node data5:4-TOLM data9:80-dram_rule[20] data89:80-interleave_list[20] | 2 |
| TAD(2) | data1:1-socket data2:1-resv data3:2-ha data5:4 – HaSYSDEFAULTURE data9:4 – HaSYSDEFAULTURE2 data13:48 – TadWayness[12] data61:4 – MacMtr | - | |
| RIR(3) | data1:1-socket data2:1-channel data3:2-imc data5:20 – imcRIRWaynessLimit[5] data25:160 – imcRIRIlv0Offset[5][8] data185:48 – imcTADChnIlvOffset[12] | - | |
| SAD_REG_PURLEY_COMM (0x10,PURLEY) | data1:1-socket data2:1-resv data3:2 – imcInterBitmap data5:4-tolm data9:128-mcRouteTable[4][8] data137:48-reserved | - | |
| SAD_REG_PURLEY_CHA (0x11,PURLEY) | data1:1-socket data2:3-resv data5:96-cboDramRule[24] data101:128-CHAInterleaveListCfg[24]; | - | |
| SAD_REG_PURLEY_MC (0x12,PURLEY) | data1:1-socket data2:3-resv data5:96-mcFMDramRule[24] data101:128-MCInterleaveListCfg[24]; | - | |
| SAD_REG_PURLEY_NM (0x13,PURLEY) | data1:1-socket data2:3-resv data5:96-mcNMDramRule[24] data101:128-MCNMInterleaveListCfg[24]; | - | |
| TAD_REG_PURLEY (0x20,PURLEY) | data1:1 – socket data2:1-resv data3:2-imc data5:32 – tadWayness data37:32 – tadbase data69:4 – mcMtr data73:4 – modeM2mem data77:4 – mirrorChnls data81:4 – mirrorFailover data85:48-reserved | - | |
| MEM_RIR_REG_PURLEY_COMM (0x30,PURLER) | data1:1 – socket data2:1-channel data3:2-imc data5:16 – imcRIRWaynessLimit[4] data21:128 – imcRIRIlv0Offset[4][8] data149:32 – imcTADChnIlvOffset[8] data181:12-dimmmtr[3] data193:24-reserved | - | |
| RIR_REG_PURLEY_FM (0x31,PURLER) | data1:1 – socket data2:1-channel data3:2-imc data5:16 – imcFMRIRWaynessLimit[4] data21:32 – imcFMRIRIlvOffset[4][2] data53:32 – fmTADChnIlvoffset[8] | - | |
| ADDDC_REG_PURLEY (0x32,PURLER) | data1:1 – socket data2:1-channel data3:2-imc data5:4-sparing_control data9:4-mcMtr data13:16 – adddc_region_control[4] data29:48 – reserved | - | |
| 0x40-SAD COMM | data1:1-socket data2:3-reserved data5:4-tolm data9:4-BLOCK_DECODER_ADDR_N0_CHABC_SAD1_REG data13:4-BLOCK_DECODER_ADDR_N1_CHABC_SAD1_REG data17:[82]-BLOCK_DECODER_EN_CFG_CHABC_SAD1_REG[8] //CFG_0~CFG_7 data33:[144] mRemoteDramRuleCfgN0[14] data89:[14*4]-mRemoteDramRuleCfgN1[14] data145:48-reserved | - | |
| 0X41-SAD CHA | data1:1-socket data2:3-reserved data5:[164] mDramRuleCfgCha[16] data69:[164] mInterleaveListCfgCha[16] data133:48-reserved | - | |
| 0X42-SAD MC | data1:1-socket data2:3-reserved data5:4-DRAM_MC_TARGET_CHABC_SAD_REG data9:4-DRAM_MC_CHANNEL_CHABC_SAD_REG data13:4-DRAM_GLOBAL_INTERLEAVE_CHABC_SAD_REG data17:[224]-mDramRt0ModeOffset[2][2] data33:[224]-mDramRt1ModeOffset[2][2] data49:[2*4]-mDramRt2ModeOffset[2] data57:104-reserved | - | |
| 0x43-SAD SNC | data1:1-Socket data2:3-reserved data5:4-CHA_SNC_CONFIG_CHA_PMA_REG data9:4-UMA_CLUSTER_CONFIG_IIO_VTD_REG data13:4-SNC_UPPER_BASE_IIO_VTD_REG data17:[54]-mIioSncBaseRegisterOffset[5] data37:[2424]-mDramTgtRouteTable[cluster][4][2] //cluster=2. If only one cluster is configured, set the unused cluster array to 0. data101:[2324]-mDramChRouteTable[cluster][3][2] //cluster=2. If only one cluster is configured, set the unused cluster array to 0. data101:[2324]-mDramChRouteTable[cluster][3][2] //cluster==2: If only one cluster is configured, set the unused cluster array to 0. data149:48-Reserved data149:48-Reserved | - | |
| 0x44-SAD MC RuleCFG | data1:1 – socket data2:1-channel data3:2-iMC data5:[84]-mMcDramRuleCfgN0[8] data37:[84] – mMcDramRuleCfgN1[8] data69:48-Reserved | - | |
| 0x50-TAD | data1:1 – socket data2:1-reserved data3:2 – iMC data5:4-reserved data9:4 – MIRRORFAILOVER data13:4-MIRRORCHNLS The data17:[20*8] – SAD2TAD[20] // is obtained by writing to the TAD_RD_N0_M2MEM_MAIN_REG register and then reading the TAD_RD_N0/N1_M2MEM_MAIN_REG. data177:48-Reserved | - | |
| 0x51 – TAD CH interleave | data1:1 – socket data2:1-channel data3:2 – iMC data5:[124] – TadChnIlvOffsetN0[12] data53:[124]-TadChnIlvOffsetN1[12] data101:4-MCNMCACHINGINTLV_MC_2LM_REG data105:4-MCNMCACHINGOFFSET_MC_2LM_REG data109:4-MCNMCACHINGCFG_MC_2LM_REG data113:48-Reserved | - | |
| 0x60-RIR BASE | data1:1 – socket data2:1-channel data3:2-iMC data5:4 – mcMtr data9:[24] – DimmMtrOffset[2] data17:4 – AMAP_MC_MAIN_REG data21:[44] – RirWaynessLimit[4] data37:[484] – RirIlvOffset[4][8] data165:[44]-FmRirWaynessLimit[4] data181:[42*4]-FmRirIlvOffset[4][2] data213:16-Reserved | - | |
| 0X61-ADDDC region | data1:1-socket data2:1-channel data3:2-iMC data5:4-sparing_control data9:4 – mcMtr data13:4-adddc_region0_control data17:4-adddc_region1_control data21:4-adddc_region2_control data25:4-adddc_region3_control data29:1-ADDDC_REGION0_MCDDC_DP_REG data30:1-ADDDC_REGION1_MCDDC_DP_REG data31:1-ADDDC_REGION2_MCDDC_DP_REG data32:1-ADDDC_REGION3_MCDDC_DP_REG data33:48-Reserved | - | |
| 0x70-Platform | data1:4-VGA_RAM_BASE data5:4-VGA_RAM_Limit data9:4-mMmCfgBase data13:4-mMmCfgLimit data17:4-mPlatGlobalMmiolBase //low base data21:4-mPlatGlobalMmiolLimit data25:8-mPlatGlobalMmiohBase //high Base data33:8-mPlatGlobalMmiohLimit data41:4-MESEGBase //ME segment address space data45:4-MESEGLimit data49:4-TSEGBase //TSEG segment address space data53:4-TSEGLimit data57:8-tolm //The upper four bytes are filled with 0. data65:8-tohm data73:1-mTotCHA //Number of CHAs of the current CPU data74:47-reserved | - | |
| HHA_INTLV (0x80) | data1:1-socket //0~3 data2:1-totem //Totem number, not a sequence number. TotemA is 1, and totemB is 3. data3:2-reserved data5:4-intlv_addr_cfg data9:48-msd_ctrl data41:48-msd_map | - | |
| DDRC_INTLV (0x81) | data1:1-socket //0~3 data2:1-ddrc //0~7 data3:2-reserved data5:4-work_mode3 data9:4-ddr_mode data13:4-work_mode_dimm data17:4-rank_vol0 data21:4-rank_vol1 data25:4-rasc_mode | - | |
| Reporting memory address information ends in the startup phase. | N/A | N/A | 3 |
| Updating memory address information is complete during hot swap. | N/A | N/A | 4 |
Table 4 MultiSystem Memory Space Info Parameter
| Soc Id | Memory Controller Type | State | Data Type | Data |
|---|---|---|---|---|
| 3 | 0-DDRC | 1- start to report | N/A | N/A |
| 2- reporting | 1-DDRC_INTLV | data1:1-socket data2:[14]-COM_MSD_EN data6:[84]-COM_MSD_CTRL[8] data38:[84]-COM_MSDDMCMAP_TA[8] data70:[84]-COM_MSDDMCMAP_TB[8] data102:[84]-COM_MSDDMCMAP_TC[8] data134:[44]-COM_MSDSKTMAP[4] data150:[14]-COM_DDR_INTLV_ADDR data154:[84]-reserved | ||
| 2- reporting | 2- Memory Address Matrix | data1:1-socket data2:1-die: TA=0, TB=3 data3: 1-channel: local channel. Each TOTEM has four channels. The value ranges from 0 to 3. data4:4-offset: offset of the data to be written. The value starts from 0 and must be written in sequence. data8:4-len: length of the written data data9:[8*N]-AddrMatric[N] | ||
| 3- end reporting | N/A | N/A |
Table 5 MultiSystem Address Config Info Parameter
| Address Type | Address Type | Data |
|---|---|---|
| 1-TF space | TF address segment | data1:8-BaseAddr: TF start address data9:8-AddrLen: TF address range length |
| 2-HBM Mirror Window and Address Range | HBM image path Range | data1:1-socket data2:1-die data3: 1-WorkingMode: working mode configuration; 6 or 9: PG; 15: AG data4: 1-TotalMirrorWindowNum: number of active/standby mirror windows data5: 1-WindowIndex, window index, numbered from 0 data6:1-MasterAddrRangeNum: number of address ranges in the primary area, starting from 1 (example: 2) data7:1-SparingAddrRangeNum: number of address ranges in the standby area, starting from 1 (example: 1) data8:8-BaseAddr: start address for main area 1 of window 0 data16:8-AddrLen data24:8-BaseAddr: start address for main area 2 of window 0 data32:8-AddrLen data40:8-BaseAddr: start address of standby area 1 of window 0 data48:8-AddrLen ... data n:1-WindowIndex n, window n data n:1-MasterAddrRangeNum: number of address ranges in the main area of window n (example 1) data n:1-SparingAddrRangeNum: number of address ranges for the standby area of window n (example 1) data n:8-BaseAddr: start address of main area 1 in window n data n:8-AddrLen data n:8-BaseAddr: start address of standby area 1 in window n data n:8-AddrLen |
Table 6 Bios Report Memory RAS Resource
| Source Type | Resource | Data |
|---|---|---|
| 0 | ACLS | data1:1-socket data2:1-logical channel // Logical channel Total number of data3:1-SubChannel0 ACLS total // SubChannel0 ACLS resources Remaining data4:1-SubChannel0 ACLS current // SubChannel0 ACLS resources Total number of data5:1-SubChannel1 ACLS total // SubChannel1 ACLS resources Remaining data6:1-SubChannel1 ACLS current // SubChannel1 ACLS resources ... //The message contains data of multiple channels. data6n+1:1-socket data6n+2:1-logical channel // logical channel Total number of data6n+3:1-SubChannel0 ACLS total // SubChannel0 ACLS resources Remaining data6n+4:1-SubChannel0 ACLS current // SubChannel0 ACLS resources Total number of data6n+5:1-SubChannel1 ACLS total // SubChannel1 ACLS resources Remaining data6n+6:1-SubChannel1 ACLS current // SubChannel1 ACLS resources |
| 1 | sPPR | data1:1 – cpu data2:1 – logical channel //Logical channel data3:1 – dimm0 sPPR granularity; 0:Bank, 1:BankGroup // dimm0 sPPR resource granularity data4:1 – dimm1 sPPR granularity; 0:Bank, 1:BankGroup // dimm1 sPPR resource granularity ...//The message contains data of multiple channels. data4n+1:1 – cpu data4n+2:1 – logical channel // logical channel data4n+3:1 – dimm0 sPPR granularity; 0:Bank, 1:BankGroup // dimm0 sPPR resource granularity data4n+4:1 – dimm1 sPPR granularity; 0:Bank, 1:BankGroup // dimm1 sPPR resource granularity |
Command Example
Set the bus size.
Request:
bash
ipmicmd -k "0f 00 30 92 db 07 00 17 00 01 00" smi 0Response:
text
0f 31 00 92 c1